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1 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash
16Gb NAND FLASH
HY27UH08AG5B
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 0.2 / Jan. 2008 1
1 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash
Document Title
16Gbit (2Gx8bit) NAND Flash Memory Revision History
Revision No.
0.0 Initial Draft. 1) Correct Cache Read figure 0.1 2) Correct Block Erase 3) Correct Multiplane operation 0.2 1) Delete Preliminary Jan. 16. 2007 Jun. 27. 2007 Preliminary
History
Draft Date
Jun. 22. 2007
Remark
Preliminary
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1 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash FEATURES SUMMARY
HIGH DENSITY NAND FLASH MEMORIES - Cost effective solutions for mass storage applications MULTIPLANE ARCHITECTURE - Array is split into two independent planes. Parallel Operations on both planes are available, halving Program and erase time. NAND INTERFACE - x8 bus width. - Address/ Data Multiplexing - Pinout compatiblity for all densities SUPPLY VOLTAGE - 3.3V device : Vcc = 2.7 V ~3.6 V MEMORY CELL ARRAY - x8 : (2K + 64) bytes x 64 pages x 16384 blocks PAGE SIZE - (2K + 64 spare) Bytes BLOCK SIZE - (128K + 4Kspare) Bytes PAGE READ / PROGRAM - Random access : 25us (max.) - Sequential access : 25ns (min.) - Page program time : 200us (typ.) - Multi-page program time (2 pages) : 200us (Typ) COPY BACK PROGRAM - Automatic block download without latency time FAST BLOCK ERASE - Block erase time: 1.5ms (Typ) - Multi-block erase time (2 blocks) : 1.5ms (Typ) STATUS REGISTER - Normal Status Register (Read/Program/Erase) - Extended Status Register (EDC) ELECTRONIC SIGNATURE - 1st cycle : Manufacturer Code - 2nd cycle : Device Code - 3rd cycle : Internal chip number, Cell Type, Number of Simultaneously Programmed Pages. - 4th cycle : Page size, Block size, Organization, Spare size - 5th cycle : Multiplane information CHIP ENABLE DON'T CARE - Simple interface with microcontroller HARDWARE DATA PROTECTION - Program/Erase locked during Power transitions. DATA RETENTION - 100,000 Program/Erase cycles (with 1bit/528byte ECC) - 10 years Data Retention PACKAGE - HY27UH08AG5B-T(P) : 48-Pin TSOP1 (12 x 20 x 1.2 mm) - HY27UH08AG5B-T (Lead) - HY27UH08AG5B-TP (Lead Free)
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1.SUMMARY DESCRIPTION
Hynix NAND HY27UH08AG5B Series have 2048Mx8bit with spare 64Mx8 bit capacity. The device is offered in 3.3 Vcc Power Supply, and with x8 I/O interface Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. The device contains 16384 blocks, composed by 64 pages. A program operation allows to write the 2112-byte page in typical 200us and an erase operation can be performed in typical 1.5ms on a 128K-byte block. Data in the page can be read out at 25ns cycle time per byte(x8). The I/O pins serve as the ports for address and data input/output as well as command input. This interface allows a reduced pin count and easy migration towards different densities, without any rearrangement of footprint. Commands, Data and Addresses are synchronously introduced using CE, WE, RE ALE and CLE input pin. The on-chip Program/Erase Controller automates all read, program and erase functions including pulse repetition, where required, and internal verification and margining of data. The modify operations can be locked using the WP input. The output pin R/B (open drain buffer) signals the status of the device during each operation. In a system with multiple memories the R/B pins can be connected all together to provide a global status signal. The copy back function allows the optimization of defective blocks management. when a page program operation fails the data can be directly programmed in another page inside the same array section without the time consuming serial data insertion phase. Copy back operation automatically executes embedded error detection operation: 1 bit error every 528byte (x8) can be detected. Due to this feature, it is no more nor necessary nor recommended to use external 2bit ECC to detect copy back operation errors. Data read out after copy back read (both for single and multiplane cases) is allowed. Even the write-intensive systems can take advantage of the HY27UH08AG5B Series extended reliability of 100K program/ erase cycles by supporting ECC (Error Correcting Code) with real time mapping-out algorithm. The chip supports CE don't care function. This function allows the direct download of the code from the NAND Flash memory device by a microcontroller, since the CE transitions do not stop the read operation. This device includes also extra features like OTP/Unique ID area, Read ID2 extension. The HY27UH08AG5B Series are available in 48-TSOP1 12 x 20 mm.
1.1 Product List
PART NUMBER HY27UH08AG5B ORGANIZATION x8 Vcc RANGE 2.7V ~ 3.6V PACKAGE 48-TSOP1
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1 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash
Figure1: Logic Diagram
IO7 - IO0 CLE ALE CE1, CE2 RE WE WP R/B1, R/B2 Vcc Vss NC
Data Input / Outputs Command latch enable Address latch enable Chip Enable Read Enable Write Enable Write Protect Ready / Busy Power Supply Ground No Connection
Table 1: Signal Names
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Figure 2. 48TSOP1 Contact, x8 Device
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1.2 PIN DESCRIPTION Pin Name IO0-IO7 Description DATA INPUTS/OUTPUTS The IO pins allow to input command, address and data and to output data during read / program operations. The inputs are latched on the rising edge of Write Enable (WE). The I/O buffer float to High-Z when the device is deselected or the outputs are disabled. COMMAND LATCH ENABLE This input activates the latching of the IO inputs inside the Command Register on the Rising edge of Write Enable (WE). ADDRESS LATCH ENABLE This input activates the latching of the IO inputs inside the Address Register on the Rising edge of Write Enable (WE). CHIP ENABLE This input controls the selection of the device. When the device is busy CE1, CE2 low does not deselect the memory. WRITE ENABLE This input acts as clock to latch Command, Address and Data. The IO inputs are latched on the rise edge of WE. READ ENABLE The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one. WRITE PROTECT The WP pin, when Low, provides an Hardware protection against undesired modify (program / erase) operations. READY BUSY The Ready/Busy output is an Open Drain pin that signals the state of the memory. SUPPLY VOLTAGE The Vcc supplies the power for all the operations (Read, Write, Erase). GROUND NO CONNECTION
CLE
ALE
CE1, CE2
WE
RE
WP R/B1,R/B2 Vcc Vss NC
Table 2: Pin Description
NOTE: 1. A 0.1uF capacitor should be connected between the Vcc Supply Voltage pin and the Vss Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations. 2. An internal voltage detector disables all functions whenever VCC is below 1.8V (3.3V version) or 1.1V (1.8V) version to protect the device from any involuntary program/erase during power transitions.
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IO0 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle A0 A8 A12 A20 A28
IO1 A1 A9 A13 A21 A29
IO2 A2 A10 A14 A22 A30
IO3 A3 A11 A15 A23 L(1)
IO4 A4 L(1) A16 A24 L(1)
IO5 A5 L
(1)
IO6 A6 L
(1)
IO7 A7 L(1) A19 A27 L(1)
A17 A25 L(1)
A18 A26 L(1)
Table 3: Address Cycle Map(x8)
NOTE: 1. L must be set to Low.
FUNCTION READ1 READ FOR COPY-BACK READ ID RESET PAGE PROGRAM COPY BACK PGM MULTI PLANE PROGRAM MULTI PLANE COPYBACK PROGRAM BLOCK ERASE MULTI PLANE BLOCK ERASE READ STATUS REGISTER RANDOM DATA INPUT RANDOM DATA OUTPUT READ CACHE (RANDOM) READ CACHE (SEQUENTIAL) READ CACHE END READ EDC STATUS REGISTER
1st CYCLE 00h 00h 90h FFh 80h 85h 80h 85h 60h 60h 70h 85h 05h 00h 31h 3Fh 7Bh
2nd CYCLE 30h 35h 10h 10h 11h 11h D0h 60h E0h 31h -
3rd CYCLE 81h 81h D0h -
4th CYCLE 10h 10h -
Acceptable command during busy
Yes
Yes
Table 4: Command Set
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CLE H L H L L L L X X X X
ALE L H L H L L L X X X X
CE L L L L L L(1) L X X X H
WE Rising Rising Rising Rising Rising H H X X X X
RE H H H H H Falling H X X X X
WP X X H H H X X H H L 0V/Vcc Read Mode
MODE Command Input Address Input(5 cycles) Command Input Address Input(5 cycles)
Write Mode Data Input
Sequential Read and Data Output During Read (Busy) During Program (Busy) During Erase (Busy) Write Protect Stand By
Table 5: Mode Selection
NOTE: 1. With the CE high during latency time does not stop the read operation
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2. BUS OPERATION
There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input, Data Output, Write Protect, and Standby. Typically glitches less than 3ns on Chip Enable, Write Enable and Read Enable are ignored by the memory and do not affect bus operations. 2.1 Command Input. Command Input bus operation is used to give a command to the memory device. Command are accepted with Chip Enable low, Command Latch Enable High, Address Latch Enable low and Read Enable High and latched on the rising edge of Write Enable. Moreover for commands that starts a modify operation (write/erase) the Write Protect pin must be high. See Figure 4 and Table 12 for details of the timings requirements. Command codes are always applied on IO7:0 regardless of the bus configuration. (x8) 2.2 Address Input. Address Input bus operation allows the insertion of the memory address. Five cycles are required to input the addresses for the 8Gbit devices. Addresses are accepted with Chip Enable low, Address Latch Enable High, Command Latch Enable low and Read Enable High and latched on the rising edge of Write Enable. Moreover for commands that starts a modifying operation (write/erase) the Write Protect pin must be high. See Figure 5 and Table 12 for details of the timings requirements. Addresses are always applied on IO7:0 regardless of the bus configuration (x8). 2.3 Data Input. Data Input bus operation allows to feed to the device the data to be programmed. The data insertion is serial and timed by the Write Enable cycles. Data are accepted only with Chip Enable low, Address Latch Enable low, Command Latch Enable low, Read Enable High, and Write Protect High and latched on the rising edge of Write Enable. See Figure 6 and Table 12 for details of the timings requirements. 2.4 Data Output. Data Output bus operation allows to read data from the memory array and to check the status register content, the EDC register content and the ID data. Data can be serially shifted out by toggling the Read Enable pin with Chip Enable low, Write Enable High, Address Latch Enable low, and Command Latch Enable low. See Figure 7,8,10,11,12 and Table 12 for details of the timings requirements. 2.5 Write Protect. Hardware Write Protection is activated when the Write Protect pin is low. In this condition modifying operation does not start and the content of the memory is not altered. Write Protect pin is not latched by Write Enable to ensure the protection even during the power up. 2.6 Standby In Standby mode the device is deselected, outputs are disabled and Power Consumption is reduced.
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3. DEVICE OPERATION
3.1 Page Read. This operation is operated by writing 00h and 30h to the command register along with five address cycles. Two types of operations are available: random read, serial page read. The random read mode is enabled when the page address is changed. The 2112 bytes (x8) of data within the selected page are transferred to the data registers in less than 25us(tR). The system controller may detect the completion of this data transfer (tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may be read out in 25ns cycle time by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make the device output the data starting from the selected column address up to the last column address. The device may output random data in a page instead of the sequential data by writing random data output command. The column address of next data, which is going to be out, may be changed to the address which follows random data output command. Random data output can be operated multiple times regardless of how many times it is done in a page. 3.2 Page Program. The device is programmed by page. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 8 times. The addressing should be done on each pages in a block. A page program cycle consists of a serial data loading period in which up to 2112bytes of data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. The serial data loading period begins by inputting the Serial Data Input command (80h), followed by the five cycle address inputs and then serial data. The bytes other than those to be programmed do not need to be loaded. The device supports random data input in a page. The column address of next data, which will be entered, may be changed to the address which follows random data input command (85h). Random data input may be operated multiple times regardless of how many times it is done in a page. The Page Program confirm command (10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal write state controller automatically executes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit (I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit (I/O 0) may be checked. The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register. Figure 14 details the sequence.
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3.3 Multi Plane Program. Device supports multiple plane program: it is possible to program in parallel 2 pages, one per each plane. A multiple plane program cycle consists of a double serial data loading period in which up to 4224bytes of data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. The serial data loading period begins by inputting the Serial Data Input command (80h), followed by the five cycle address inputs and then serial data for the 1st page. Address for this page must be within 1st plane (A<18>=0). The data of 1st page other than those to be programmed do not need to be loaded. The device supports random data input exactly like page program operation. The Dummy Page Program Confirm command (11h) stops 1st page data input and the device becomes busy for a short time (tDBSY). Once it has become ready again, 81h command must be issued, followed by 2nd page address (5 cycles) and its serial data input. Address for this page must be within 2nd plane (A<18>=1). The data of 2nd page other than those to be programmed do not need to be loaded. Program Confirm command (10h) makes parallel programming of both pages start. User can check operation status by R/B pin or read status register command, as if it were a normal page program; status register command is also available during Dummy Busy time (tDBSY). In case of fail in 1st or 2nd page program, fail bit of status register will be set: Device supports pass/fail status of each plane. Figure 19 details the sequence. 3.4 Block Erase. The Erase operation is done on a block basis. Block address loading is accomplished in there cycles initiated by an Erase Setup command (60h). Only address A18 to A30 is valid while A12 to A17 is ignored (x8). The Erase Confirm command (D0h) following the block address loading initiates the internal erasing process. This two step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase verify. Once the erase process starts, the Read Status Register command may be entered to read the status register. The system controller can detect the completion of an erase by monitoring the R/B output, or the Status bit (I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while erasing is in progress. When the erase operation is completed, the Write Status Bit (I/O 0) may be checked. Figure 18 details the sequence. 3.5 Multi Plane Erase. Multiple plane erase, allows parallel erase of two blocks, one per each memory plane. Block erase setup command (60h) must be repeated two times, each time followed by 1st block and 2nd block address respectively (3 cycles each). As for block erase, D0h command makes embedded operation start. Multiplane erase does not need any Dummy Busy Time between 1st and 2nd block address insertion. Address limitation required for multiple plane program applies also to multiple plane erase, as well as operation progress can be checked like for multiple plane program. Figure 20 details the sequence
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1 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash
3.6 Copy-back Program Copy-Back program with Read for Copy-Back is configured to quickly and efficiently rewrite data stored in one page without data reloading when the bit error is not in data stored. Since the time-consuming re-loading cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also needs to be copied to the newly assigned free block. Copy-Back operation is a sequential execution of Read for Copy-Back and of copy-back program with the destination page address. A read operation with "35h" command and the address of the source page moves the whole 2,112-byte data into the internal data buffer. A bit error is checked by sequential reading the data output. In the case where there is no bit error, the data do not need to be reloaded. Therefore Copy-Back program operation is initiated by issuing Page-Copy Data-Input command (85h) with destination page address. Actual programming operation begins after Program Confirm command (10h) is issued. Once the program process starts, the Read Status Register command (70h) may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. When the Copy-Back Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 16 & Figure 17). The command register remains in Read Status command mode until another valid command is written to the command register. During copy-back program, data modification is possible using random data input command (85h) as shown in Figure17. Copy-back program operation is allowed only within same plane. 3.7 Multi-Plane Copy-Back Program The copy-back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an external memory. Since the time-consuming cycles of serial access and re-loading cycles are removed, the system performance is greatly improved. The benefit is especially obvious when a portion of a block needs to be updated and the rest of the block also need to be copied to the newly assigned free block. The operation for performing a copy-back program is a sequential execution of page-read without serial access and copying-program with the address of destination page. A read operation with "35h" command and the address of the source page moves the whole 2112byte data into the internal data buffer. As soon as the device returns to Ready state, optional data read-out is allowed by toggling RE (See Figure 21), or Copy Back command (85h) with the address cycles of destination page may be written. The Program Confirm command (10h) is required to actually begin the programming operation. Data input cycle for modifying a portion or multiple distant portions of the source page is allowed as shown in Figure 21. Most NAND devices require 2 bit external ECC only due to copy back operation while 1 bit ECC can be enough for all other operation. Reason is that during read for copy back + copy back program sequence a bit error due to charge loss is not checked by external error detection/correction scheme. On the contrary, 16Gbit NAND includes automatic Error Detection Code during copy back operation: thanks to this, 2 bit external ECC is no more required, with significant advantage for customers that can always use single bit ECC. More details on EDC operation are available in section 3.8.
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1 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash
3.8 EDC Operation Error Detection Code check automatically starts immediately after device becomes busy for a copy back program operation (both single and multiple plane). In the x8 version EDC allows detection of 1 single bit error every 528 bytes, where each 528byte group is compdsed by 512 bytes of main array and 16 bytes of spare area (see Table 19) So described 528byte area is called "EDC unit". To Properly use EDC, some limitations apply: - Random data input can be used only once in copy back program or page program or multiple page program, unless user inputs data for a whole EDC unit (or more whole EDC units). - Any page program operation must be done on whole page basis, or on whole EDC unit (s). EDC result can be checked only during copy back program through 7Bh (specific Read EDC register command, Table 20) 3.9 Read Status Register. The device contains a Status Register which may be read to find out whether, program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to table 13 for specific Status Register definitions. The command register remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random data output, the read command (00h) should be given before starting read cycles. 3.10 Read EDC Status Register The operation is available only in copy back program and it allows the detection of errors occurred during read for copy back. In case of multiple plane copy back, it is not possible to know which of the two read operation caused the error. After writing 7Bh command to the command register, a read cycle outputs the content of the EDC Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. Operation is same read status register command. Refer to below Table 20 for specific EDC Register definitions. 3.11 Read ID. The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Five read cycles sequentially output the manufacturer code (ADh), and the device code and 3rd, 4th, 5th cycle ID, respectively. The command register remains in Read ID mode until further commands are issued to it. Figure 22 shows the operation sequence, while tables 14 explain the byte meaning. 3.12 Reset. The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared to value C0h when WP is high. Refer to table 13 for device status after reset operation. If the device is already in reset state a new reset command will not be accepted by the command register. The R/B pin goes low for tRST after the Reset command is written. Refer to Figure 25.
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1 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash
3.13 Cache Read Cache read operation allows automatic download of consecutive pages. Immediately after 1st latency end, while user can start reading out data, device internally starts reading following page. Start address of 1st page is at page start (A<10:0>=00h), after 1st latency time (tr) , automatic data download will be uninterrupted. In fact latency time is 25us, while download of a page require at least 100us for x8 device. (50us for x16device). The Cache Read function may be issued after the Read function is complete (SR[6] is set to one). The host may enter the address of the next page to be read from the Flash array. Data output always begins at column address 00h. If the host does not enter an address to retrieve, the next sequential page is read. When the Cache Read function is issued, SR[6] is cleared to zero (busy). After the operation is begun SR[6] is set to one (ready) and the host may begin to read the data from the previous Read or Cache Read function. Issuing an additional Cache Read function copies the data most recently read from the array into the page register. When no more pages are to be read, the final page is copied into the page register by issuing the 3Fh command. The host may begin to read data from the page register when SR[6]is set to one (ready). When the 31h and 3Fh commands are issued, SR[6] shall be cleared to zero (busy) until the page has finished being copied from the Flash array. The host shall not issue a sequential Read Cache (31h) command after the last page of the device is read. Refer to Figure 13. Cache Read operation must be done only block by block if system needs to avoid reading also reading from invalid blocks.
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4. OTHER FEATURES
4.1 Data Protection & Power On/Off Sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 2.0V(3.3V device). WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 10us is required before internal circuit gets ready for any command sequences as shown in Figure 26. The two-step command sequence for program/erase provides additional software protection. 4.2 Ready/Busy. The device has a Ready/Busy output that provides method of indicating the completion of a page program, erase, copy-back and random read completion. The R/B pin is normally high and goes to low when the device is busy (after a reset, read, program, erase operation). It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tR(R/B) and current drain during busy (Ibusy), an appropriate value can be obtained with the following reference chart (Fig 27). Its value can be determined by the following guidance.
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Parameter Valid Block Number
Symbol NVB
Min 16064
Typ -
Max 16384
Unit Blocks
Table 6 : Valid Blocks Numbers
NOTE: 1. The 1st block is guaranteed to be a valid block at the time of shipment. 2. The number of valid blocks is for single plane & multi-plane operations. 3. Each chip has maximum 80 invalid blocks.
Symbol TA TBIAS TSTG VIO(2) Vcc
Parameter Ambient Operating Temperature (Commercial Temperature Range) Ambient Operating Temperature (Industrial Temperature Range) Temperature Under Bias Storage Temperature Input or Output Voltage Supply Voltage
Value 0 to 70 -40 to 85 -50 to 125 -65 to 150 -0.6 to 4.6 -0.6 to 4.6
Unit V V V
Table 7: Absolute maximum ratings
NOTE: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the Hynix SURE Program and other relevant quality documents. 2. Minimum Voltage may undershoot to -2V during transition and for less than 20ns during transitions.
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Figure 3: Block Diagram
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Parameter Sequential Read Program Erase Stand-by Current (TTL) Stand-by Current (CMOS) Input Leakage Current Output Leakage Current Input High Voltage Input Low Voltage Output High Voltage Level Output Low Voltage Level Output Low Current (R/B)
Symbol ICC1 ICC2 ICC3 ICC4 ICC5 ILI ILO VIH VIL VOH VOL IOL (R/B)
Test Conditions tRC=25ns CE=VIL, IOUT=0mA CE=VIH, WP=0V/Vcc CE=Vcc-0.2, WP=0V/Vcc VIN=0 to Vcc (max) VOUT =0 to Vcc (max) IOH=-400uA IOL=2.1mA VOL=0.4V
3.3Volt Min 0.8xVcc -0.3 2.4 8 40 10 Typ 20 20 20 Max 40 40 40 1.5 200 40 40 Vcc+0.3 0.2xVcc 0.4 -
Unit mA mA mA mA uA uA uA V V V V mA
Operating Current
Table 8: DC and Operating Characteristics
Parameter Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load (2.7V - 3.6V)
Value 3.3Volt 0V to VCC 5ns VCC/2 1 TTL GATE and CL=50pF
Table 9: AC Conditions
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Item Input / Output Capacitance Input Capacitance
Symbol CI/O CIN
Test Condition VIL=0V VIN=0V
Min -
Max 40 40
Unit pF pF
Table 10: Pin Capacitance (TA=25C, F=1.0MHz)
Parameter Program Time / Multi-Plane Program Time Dummy Busy Time for Two Plane Program Number of partial Program Cycles in the same page Block Erase Time / Multi-Plane Block Erase Time Read Cache Busy Time
Symbol tPROG tDBSY NOP tBERS tRCBSY
Min -
Typ 200 0.5 1.5 3
Max 700 1 8 2 tR
Unit us us Cycles ms us
Table 11: Program / Erase Characteristics
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1 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash
Parameter
CLE Setup time CLE Hold time CE setup time CE hold time WE pulse width ALE setup time ALE hold time Data setup time Data hold time Write Cycle time WE High hold time Data Transfer from Cell to register ALE to RE Delay CLE to RE Delay Ready to RE Low RE Pulse Width WE High to Busy Read Cycle Time RE Access Time RE High to Output High Z CE High to Output High Z CE High to Output hold RE High to Output Hold RE Low to Output Hold RE High Hold Time Output High Z to RE low CE Low to RE Low Address to data loading time WE High to RE low RE High to WE low Device Resetting Time (Read / Program / Erase) Write Protection time
Symbol
tCLS tCLH tCS tCH tWP tALS tALH tDS tDH tWC tWH tR tAR tCLR tRR tRP tWB tRC tREA tRHZ tCHZ tCOH tRHOH tRLOH tREH tIR tCR
tADL
3.3V Min
12 5 20 5 12 12 5 12 5 25 10 25 10 10 20 12 100 25 20 100 50 15 15 5 10 0 10 70 80 100 5/10/500(1) 100
Max
Unit
ns ns ns ns ns ns ns ns ns ns ns us ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns us ns
tWHR tRHW tRST tWW
(2)
Table 12: AC Timing Characteristics
NOTE:
1. If Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5us 2. Program / Erase Enable Operation : WP high to WE High. Program / Erase Disable Operation : WP Low to WE High.
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1 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash
IO 0 1 2 3 4 5 6 7
Page Program Pass / Fail NA NA NA NA Ready / Busy Ready / Busy Write Protect
Block Erase Pass / Fail NA NA NA NA Ready / Busy Ready / Busy Write Protect
Read NA NA NA NA NA Ready / Busy Ready / Busy Write Protect
Cache Read NA NA NA NA NA P/E/R Controller Bit Ready/Busy NA
CODING Pass: `0' Fail: `1' Active: `0' Idle:'1' Busy: `0' Ready:'1' Protected: `0' Not Protected: `1'
Table 13 : Status Register Coding
DEVICE IDENTIFIER CYCLE 1st 2nd 3rd 4th 5th
DESCRIPTION Manufacturer Code Device Identifier Internal chip number, cell Type, etc. Page Size, Block Size, Spare Size, Organization Multiplane information
Table 14: Device Identifier Coding
Part Number HY27UH08AG5B
Voltage 3.3V
Bus Width x8
1st cycle (Manufacture Code) ADh
2nd cycle (Device Code) D3h
3rd cycle 51h
4th cycle 95h
5th cycle 58h
Table 15: Read ID Data Table
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1 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash
Description Die / Package 1 2 4 8
IO7
IO6
IO5 IO4
IO3 IO2
IO1 IO0 0 0 1 1 0 1 0 1
Cell Type
2 Level Cell 4 Level Cell 8 Level Cell 16 Level Cell
1 2 4 8 Not Supported Not Supported 0 1 0 1 0 0 1 1 0 1 0 1
0 0 1 1
0 1 0 1
Number of Simultaneously Programmed Pages Interleave program Between multiple chips Write Cache
Table 16: 3rd Byte of Device Idendifier Description
Description Page Size (Without Spare Area) Spare Area Size (Byte / 512Byte) Serial Access Time 1KB 2KB 4KB 8KB 8 16 50ns 30ns 25ns Reserved 64K 128K 256K 512KB X8 X16
IO7
IO6
IO5-4
IO3
IO2
IO1-0 0 0 1 1 0 1 0 1
0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1
Block Size (Without Spare Area) Organization
Table 17: 4th Byte of Device Identifier Description
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1 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash
Description Plane Number 1 2 4 8 64Mb 128Mb 256Mb Plane Size (w/o redundant Area) 512Mb 1Gb 2Gb 4Gb 8Gb Reserved
IO7
IO6 IO5 IO4
IO3 IO2 0 0 1 1 0 1 0 1
IO1
IO0
0 0 0 0 1 1 1 1 0
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 0
Table 18: 5rd Byte of Device Idendifier Description
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1 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash
Table 19: Page organization in EDC units (x8)
IO 0 1 2 3 4 5 6 7
Copy back Program Pass/Fail EDC status EDC Validity NA NA Ready/Busy Ready/Busy Write Protect
CODING Pass: Fail: `1' NO error: `0' Invalid: `0' Valid: `1' Busy: `0' Ready: `1' Busy: `0' Ready: `1' Protected: `0' Not Protected: `1'
Table 20: EDC Register Coding
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1 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash
Figure 4: Command Latch Cycle
Figure 5: Address Latch Cycle
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1 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash
Figure 6: Input Data Latch Cycle
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1 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash
Figure 7: Sequential Out Cycle after Read (CLE=L, WE=H, ALE=L)
Figure 8: Sequential Out Cycle after Read (EDO Type CLE=L, WE=H, ALE=L)
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1 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash
Figure 9: Status Read Cycle
Figure 10: Read1 Operation (Read One Page)
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1 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash
Figure 11: Read1 Operation intercepted by CE
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1 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash
Figure 12: Random Data output
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1 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash
Figure 13: Read Operation with Read Cache
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1 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash
Figure 14: Page Program Operation
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1 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash
Figure 15 : Random Data In
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1 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash
Figure 16: Copy Back Program Operation
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1 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash
Figure 17: Copy Back Program Operation with Random Data Input
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1 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash
Figure 18: Block Erase Operation (Erase One Block)
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1 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash
Figure 19: Multiple plane page program
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1 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash
Figure 20: Multiple plane erase operation
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1 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash
Figure 21: Multi plane copyback program Operation
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1 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash
Figure 22: Read ID Operation
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1 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash
System Interface Using CE don't care To simplify system interface, CE may be deasserted during data loading or sequential data-reading as shown below. So, it is possible to connect NAND Flash to a microporcessor. The only function that was removed from standard NAND Flash to make CE don't care read operation was disabling of the automatic sequential read function.
Figure 23: Program Operation with CE don't-care.
Figure 24: Read Operation with CE don't-care.
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1 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash
Figure 25: Reset Operation
Figure 26: Power On and Data Protection Timing
VTH = 2.5 Volt for 3.3 Volt Supply devices
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1 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash
Figure 27: Ready/Busy Pin electrical specifications
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1 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash
Figure 28: page programming within a block
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1 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash
Bad Block Management
Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the blocks are valid. A Bad Block does not affect the performance of valid blocks because it is isolated from the bit line and common source line by a select transistor. The devices are supplied with all the locations inside valid blocks erased(FFh). The Bad Block Information is written prior to shipping. Any block where the 1st Byte in the spare area of the 1st or 2nd th page (if the 1st page is Bad) does not contain FFh is a Bad Block. The Bad Block Information must be read before any erase is attempted as the Bad Block Information may be erased. For the system to be able to recognize the Bad Blocks based on the original information it is recommended to create a Bad Block table following the flowchart shown in Figure 29. The 1st block, which is placed on 00h block address is guaranteed to be a valid block.
Figure 29: Bad Block Management Flowchart
NOTE : 1. Make sure that FFh at the column address 2048 of the 1st page and 2nd page.
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1 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash
Bad Block Replacement
Over the lifetime of the device additional Bad Blocks may develop. In this case the block has to be replaced by copying the data to a valid block. These additional Bad Blocks can be identified as attempts to program or erase them will give errors in the Status Register. Unlike the case of odd page which carries a possibility of affecting previous page, the failure of a page program operation does not affect the data in other pages in the same block, the block can be replaced by re-programming the current data and copying the rest of the replaced block to an available valid block. Refer to Table 21 and Figure 30 for the recommended procedure to follow if an error occurs during an operation.
Operation Erase Program Read
Recommended Procedure Block Replacement Block Replacement ECC (with 1bit/528byte)
Table 21: Block Failure
Figure 30: Bad Block Replacement
NOTE : 1. An error occurs on nth page of the Block A during program or erase operation. 2. Data in Block A is copied to same location in Block B which is valid block. 3. Nth data of block A which is in controller buffer memory is copied into nth page of Block B 4. Bad block table should be updated to prevent from eraseing or programming Block A
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1 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash Write Protect Operation
The Erase and Program Operations are automatically reset when WP goes Low (tWW = 100ns, min). The operations are enabled and disabled as follows (Figure 31~34)
Figure 31: Enable Programming
Figure 32: Disable Programming
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1 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash
Figure 33: Enable Erasing
Figure 34: Disable Erasing
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1 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash
Figure 35. 48-TSOP1 - 48-lead Plastic Thin Small Outline, 12 x 20mm, Package Outline
millimeters
Min Typ Max 1.200 0.050 0.980 0.170 0.100 0.150 1.030 0.250 0.200 0.100 11.910 19.900 18.300 12.000 20.000 18.400 0.500 0.500 0 0.680 5 12.120 20.100 18.500
Symbol A A1 A2 B C CP D E E1 e L alpha
Table 22: 48-TSOP1 - 48-lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data
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1 HY27UH08AG5B Series 16Gbit (2Gx8bit) NAND Flash
MARKING INFORMATION - TSOP1
P a ck a g M a rk in g E x a m p le
K
O
R
TSO P1
H
Y
2
7
U
H
0
8
A
G
5
B
x
x
x
x
Y
W
W
x
x
- h y n ix - KOR - H Y27UH08AG5B xxxx H Y : H yn ix 2 7 : N A N D Fla sh U : P o w e r S u p p ly H : C lassifica tio n 0 8 : B it O rg a n ization A G : D e n sity 5 : M o de B : V e rsion x : P acka ge T yp e x : P acka ge M a te ria l x : O p eratin g T e m perature x : B ad B lo ck
: H yn ix S ym bo l : O rig in C ou n try : P a rt N u m b er
: U (2 .7 V ~ 3 .6 V ) : S in g le Leve l C e ll+ Q u ad ru ple D ie + Large B lo ck : 0 8 (x8 ) : 1 6 G b it : 5 (2 n C E & 2 R /n B ; S e q u e n tia l R o w R e a d D isa ble ) : 3 rd G e n era tion : T (4 8-T S O P 1 ) : B la n k(N orm a l), P (Le a d Fre e ) : C (0 ~ 7 0 ), I(-4 0 ~ 8 5 ) : B (In clu de d B a d B lock ), S (1 ~ 5 B a d B lock ), P (A ll G o od B lo ck)
- Y : Y e ar (ex: 5 = ye ar 2 0 0 5 , 6= ye a r 2 0 0 6 ) - w w : W o rk W eek (e x: 12 = w ork w eek 12 ) - x x : P roce ss C o d e N o te - C a p ita l L e tte r - S m a ll L e tte r : Fixe d Ite m : N on -fixe d Ite m
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